A method for the synthesis of asynchronous sequential machines that leads to a realisation directly obtained from the flow graph (or flow table) is described. Each state of the system is materialised with a memory element designed in such a way that the state transitions operate in a request/acknowledge mode. The consequences are that the sequential network is hazard free and only the input transfer functions need to be generated.
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Courvoisier et al. (1974) studied this question.