Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies, such as 3D stacked ICs (3D-SICs) based on through-silicon vias (TSVs). Due to their advanced manufacturing processes and physical access limitations, the complexity and cost associated with testing this type of 3D-SICs are considered major challenges. This Embedded Tutorial provides an overview of the manufacturing steps of TSV-based 3D chips and their associated test challenges. It discusses the necessary flows for wafer-level and package-level tests, the challenges with respect to test contents and wafer-level probe access, and the on-chip DfT infrastructure required for 3D-SICs.
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Marinissen et al. (2009) studied this question.
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