Simulation of switching noise in on-chip power distribution networks of FPGAs

An explicit approach has been used to simulate switching noise in on-chip power distribution networks. This approach has been extended to analyze on-chip power distribution networks of field programmable gate array (FPGA), whose power distribution network is more irregular than that of an application specific integrated circuit (ASIC). The switching noise has been compared between the on-chip power distribution networks of FPGAs and ASICs. Switching noise simulation of power/ground grids requires a static IR drop analysis before the transient simulation. The importance of performing a static IR drop analysis prior to the transient simulation has been illustrated.