Physical and predictive models of ultra thin oxide reliability in CMOS devices and circuits

This paper reviews the physics and statistics of dielectric wearout and breakdown in ultra thin SiO/sub 2/-based CMOS gate dielectrics. Electrons or holes tunneling through gate oxide generate defects until a critical density is reached and the oxide breaks down. Critical defect density is explained by defect percolation path formation across the oxide; <1% of these paths lead to destructive breakdown, and the microscopic nature of the defects is not known. Defect generation rate decreases approximately exponentially with supply voltage, below a threshold voltage of about 5 V for hot electron induced hydrogen release, but tunnel current increases exponentially with decreasing oxide thickness, giving decreasing time-to-breakdown and a lower reliability margin as device dimensions are scaled. Estimating dielectric reliability requires extrapolation from measurement conditions to operational conditions. Due to the lower reliability margin, it is imperative to reduce extrapolation error. Long term stress experiments are used to measure ultra thin dielectric film wearout and breakdown as close as possible to operating conditions, and have revealed the voltage dependence of the defect generation rate and critical defect density, allowing better time-to-breakdown voltage dependence modeling. Such measurements are used to guide pre-manufacturing technology development. We discuss electrical conduction through a breakdown spot, and the effect of oxide breakdown on device and circuit performance. In some cases, oxide breakdown does not lead to immediate circuit failure, and a quantitative methodology to predict circuit reliability must be developed.