A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 m2 SRAM cell size

A 14nm logic technology using 2 nd -generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4 th generation high-k metal gate, and 6 th -generation strained silicon, resulting in the highest drive currents yet reported for 14nm technology. This technology is in high-volume manufacturing.