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A reconfigurable transceiver capable of adapting its signaling mode to the I/O channel is implemented in 45nm CMOS. When configured for single-ended 2/3/4-PAM, it enables 5-to-25Gb/s signaling over on-package interconnect while dissipating 1.6-to-2.6mW/(Gb/s). Over a backplane channel, a differential source series-terminated signaling configuration with TX pre-emphasis and 1-tap DFE allows 10Gb/s signaling with 3.8mW/(Gb/s) power efficiency.
Balamurugan et al. (Mon,) studied this question.
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