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A 64Mb NAND-compatible non-volatile memory testchip based on a conductive metal-oxide technology is developed in 0.13μm technology. The memory cell, which does not require a selection device, occupies 0.17μm 2 and is built at the intersection of two metal lines above the CMOS circuitry. The chip uses 4 layers of cross-point arrays. Decoding and sensing techniques are also described.
Chevallier et al. (Mon,) studied this question.
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