Circuit design issues affecting present and future deep sub-micron ferroelectric random-access memories

Abstract The basic architecture of ferroelectric memories (FeRAMs) is known to be very similar to that of DRAM. Consequently, many design issues for FeRAM are already known from DRAM and have been solved by applying prior DRAM solutions. However, there are also a number of issues that are unique to FeRAM. Often these issues become critical design problems that require innovative circuit-level solutions1. This paper discusses some of the most relevant issues affecting present and future deep sub-micron FeRAMs. In addition, new problems that have to be solved for future FeRAMs are presented.