Modeling of Integrated Circuit Defect Sensitivities

Until now only cursory descriptions of mathematical models for defect sensitivities of integrated circuit chips have been given in the yield literature. This paper treats the fundamentals of the defect models that have been used successfully at IBM for a period of more than fifteen years. The effects of very small defects are discussed first. The case of photolithographic defects, which are of the same dimensions as the integrated circuit device and interconnection patterns, is dealt with in the remainder of the paper. The relationships between these models and test sites are described. Data from measurements of defect sizes are discussed.