22nm half-pitch patterning by CVD spacer self alignment double patterning (SADP)

Self-aligned double patterning (SADP) is a patterning technique that uses CVD spacers formed adjacent to a core (template) pattern that is defined by conventional lithography. After stripping the core (template) material, the spacers serve as a hardmask with double the line density of the original lithographically defined template. This integration scheme is an alternative to conventional double patterning for extending the half-pitch resolution beyond the current lithography tool's half-pitch limit. Using a positive tone (spacer as mask) approach, we show capability to create 22nm line and space arrays, on 300mm wafers, with full wafer critical dimension uniformity (CDU) < 2nm (3 sigma) and line edge roughness (LER) < 2nm. These 22nm line and space results stem from template lithography using 1.2NA 193nm water immersion lithography. In this paper, we also demonstrate lot to lot manufacturability, the patterning of two substrate types (STI and silicon oxide trench), as well as demonstrate the formation of gridded design rule (GDR) building blocks for circuit design.