Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits

In this paper we develop dynamic models for ideal three- and four-stage voltage multipliers. Starting from the models proposed, we can perform a pencil-and-paper area-efficient optimized design. The circuits discussed are commonly used in power ICs or memory ICs to allow the switching on of an MOS device. The models proposed are validated both by measurement on a breadboard and by SPICE simulation.