A review of yield modelling techniques for semiconductor manufacturing

Abstract Semiconductor manufacturing is a complex multistage manufacturing process, and wafer fabs use complex processes involving billions of dollars worth of equipment to produce integrated circuits. The level of complexities associated with an integrated circuit is increasing in terms of feature size and number of devices. Companies use several performance metrics such as defectiveness, yield, and cycle time to improve manufacturing performance. Maintaining high yield through reliable and accurate quality control measures is one of the key performance criteria used by companies. The intent of this paper is to provide a review of the literature dealing with critical aspects of yield modelling. A review of many topics from simple probabilistic yield models to the incorporation of critical features such as spatial defects and radial yield losses will be provided. We will also assess empirical techniques used to model variations associated with complex interrelated wafer manufacturing processes. We emphasize that yield modelling should not be considered in isolation and system-wide aspects are necessary for integrated yield modelling and analysis. Keywords: Yield modellingSemiconductor manufacturing Acknowledgement This work was supported by NSF/SRC/ISMI grants DMI-0432484 and DMI-0432395.