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This paper describes the core and I/O clocking architecture of the next generation Intel reg Coretrade micro-architecture processor (Nehalem), designed on a 45 nm process technology. Local PLL placement provides modularity and power-efficient scalability by allowing independent frequency and voltage domains. Fast-locking, low-skew PLLs are used to achieve 56% lock time reduction and 30% long-tem jitter improvement. Adaptive frequency, supply, and duty cycle mechanisms combine for up to 5% core frequency gain at iso-voltage. Jitter attenuating DLLs with enhanced linearity and plusmn15% duty cycle correction drive a differential, low-swing I/O receiver clock distribution, reducing jitter by 25% and enabling 25.6 GB/s Intel reg QuickPath Interconnect bandwidth and three-channel DDR3 traffic up to 32 GB/s.
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Nasser Kurd
Intel (United States)
Praveen Mosalikanti
Mark Neidengard
IEEE Journal of Solid-State Circuits
Intel (United States)
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Kurd et al. (Tue,) studied this question.
synapsesocial.com/papers/6a201026d40b4a263065c602 — DOI: https://doi.org/10.1109/jssc.2009.2014023