A low power, 10-bit CMOS D/A converter for high speed applications

In this paper, the realization of a fully binary 10-bit current steering CMOS DAC is presented. Both the measured INL and DNL are smaller than 0.2 LSB. Better than 60 dB SFDR is achieved for all output signals up to a 30 MS/s Nyquist frequency. For a 1 MHz signal, the chip achieves better than 60 dB SFDR for all update rates up to 800 MS/s. The presented DAC core occupies 0.23 mm/sup 2/. The digital power consumption is only 1 mW for a 30 MS/s Nyquist operation. Based on a fundamental theoretical INL- and DNL-yield analysis, the presented design explores the limits towards the binary and the low-power edges of the design space.