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A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.50-/spl mu/m CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm/sup 2/ and consumes a low power of 34 mW. The measured phase noise of the synthesizer is -121.8 dBc/Hz at 600-kHz offset, and the measured spurious levels are -79.5 and -82.0 dBc at 1.6 and 11.3 MHz offset, respectively.
Yan et al. (Mon,) studied this question.