A VLSI network of spiking neurons with an asynchronous static random access memory

In this paper we present an asynchronous VLSI neuromorphic architecture comprising an array of integrate and fire neurons and dynamic synapse circuits with programmable weights. To store synaptic weight values, we designed a novel asynchronous SRAM block, integrated it on chip and connected it to the dynamic synapse circuits, via a fast current-mode DAC. The control and data signals used for programming the weights into the SRAM, as well as the standard input and output signals, are encoded using the AER representation. The device acts as a transceiver, both receiving Address-Events in input and transmitting them as output spikes. The possibility of changing the synaptic weights via the AER protocol allows the flexibility of exploring different STDP learning algorithms in a mixed SW/HW setup. We provide experimental results measured from the chip that demonstrate the correct behavior of all the circuit blocks implemented on the chip.