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This paper discusses an open source, variation aware Process Design Kit (PDK), based on Scalable CMOS design rules, down to 45nm, for use in VLSI research, education and small businesses. This kit includes all the necessary layout design rules and extraction command decks to capture layout dependent systematic variation and perform statistical circuit analysis. The kit also includes a standard cell and pad library with the necessary support files to enable full chip place and route and verification for System on Chip designs. Test chips designed with this PDK are designed in such a way so that they can be fabricated by fabrication facilities allowing validation of the design rules so that the rules may be used in future multi-project runs and design contests.
Stine et al. (Fri,) studied this question.