Industrial evaluation of DRAM tests

This paper presents the results of 44 well known memory tests applied to 1896 1M*4 DRAM chips, using up to 96 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests (i. e. those covering more different functional faults) also have a higher fault coverage. However, the currently used fault models still leave much to be explained; e. g. , the used data backgrounds and address orders show an unexplainable large variation in fault coverage. 1. Contact check: Verifies DUT-memory tester contact 2. Input leakage current high (INP LKH): Verifies I I (L) -max 3. Input leakage current low (INP LKL): Verifies I I (L) -min 4. Output leakage current high (OUT LKH): Verifies I O (L) -max 5. Output leakage current low (OUT LKL): Verifies I O (L) -min 6. Operating current (ICC1): Verifies ICC1 7. Standby current (ICC2): Verifies ICC2 8. Refresh current (ICC3): Verifies ICC3 9. Data retention (4n + 6ts) Note: ts is the settling time = 5ms; Del = 1. 2 * tREF: (wcheckerb) ;Vcc Vccmin; Del; Vcc Vcc-typ; (rcheckerb). Repeat test for data-complement 10. Volatility (6n + 6ts): (wcheckerb) ;Vcc Vcc-min; (rcheckerb) ; Vcc Vcc-typ; (rcheckerb). Repeat test for data-complement 11. Vcc R/W (8n + 6ts): Vcc Vcc-max; (wd) ; Vcc Vcc-min; (rd) ; (wd) ; Vcc Vcc-max; (rd). Repeat for d = d * 2. March tests. March tests are very popular tests for functional faults such as address decoder faults, coupling faults, etc 5. The notation used for these tests is as follows: denotes an increasing address order, denotes a decreasing address order, while denotes that the to be used address order can be chosen arbitrarily to be or. Some tests occur in different versions, such as March Cand March C -R, because, for experimentation purposes, extra read operations have been added to the march elements. 'D' denotes the delay time for DRFs. 12. Scan (4n): (w0) ; (r0) ; (w1) ; (r1) 13. Mats+ (5n): (w0) ; (r0, w1) ; (r1, w0) 14. Mats++ (6n): (w0) ; (r0, w1) ; (r1, w0, r0) 15. March A (15n): (w0) ; (r0, w1, w0, w1) ; (r1, w0, w1) ; (r1, w0, w1, w0) ; (r0, w1, w0) 16. March B (17n): (w0) ; (r0, w1, r1, w0, r0, w1) ; (r1, w0, w1) ; (r1, w0, w1, w0) ; (r0, w1, w0) 17. March C- (10n): (w0) ; (r0, w1) ; (r1, w0) ; (r0, w1) ; (r1, w0) ; (r0) 18. March C-R (15n): (w0) ; (r0, r0, w1) ; (r1, r1, w0) ; (r0, r0, w1) ; (r1, r1, w0) ; (r0, r0) 19. PMOVI (13n): (w0) ; (r0, w1, r1) ; (r1, w0, r0) ; (r0, w1, r1) ; (r1, w0, r0) 20. PMOVI-R (17n): (w0) ; (r0, w1, r1, r1) ; (r1, w0, r0, r0) ; (r0, w1, r1, r1) ; (r1, w0, r0, r0) 21. March G (23n + 2D): (w0) ; (r0, w1, r1, w0, r0, w1) ; (r1, w0, w1) ; (r1, w0, w1, w0) ; (r0, w1, w0) ; D; (r0, w1, r1) ; D; (r1, w0, r0) 22. March U (13n): (w0) ; (r0, w1, r1, w0) ; (r0, w1) ; (r1, w0, r0, w1) ; (r1, w0) 23. March UD (13n + 2D): (w0) ; (r0, w1, r1, w0) ; D; (r0, w1) ; D; (r1, w0, r0, w1) ; (r1, w0) 24. March U-R (15n): { (w0) ; (r0, w1, r1, r1, w0) ;