Investigation of Residual Stress in Wafer-Level Interconnect Structures Induced by Wafer Processing

Wafer processing induced residual stress in wafer level Cu interconnect structures can have a significant impact on reliability of Cu interconnects. In this study, a finite element analysis approach based on element birth and death technique was developed to simulate the wafer processing procedure. Residual stress in the wafer structures at each processing step was obtained. Wafer processing procedures for Cu single damascene structures were first simulated and the results were verified with stresses measured by X-ray techniques. After the FEA model was verified, Cu dual damascene structures were studied in detail. Residual stress obtained from FEA was used to explain the stress-induced voiding phenomenon at the bottom of via after wafer processing.