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Thermo-mechanical simulation is carried out on the Cu/low-k FCBGA (flip-chip ball grid array) package for high performance server applications. Global-local modeling methodology is performed. Layered structures for both buildup substrate and Cu/low-k layers are established. The buildup substrate is divided into inner and outer areas based on the Cu distribution, and equivalent properties for each area are obtained. A homogenization method which enables to take exact Cu/low-K layout into account is developed to obtain the equivalent properties of interconnects. Furthermore, faithful simulation of the consecutive material deposit steps has been performed in order to reproduce the whole fabrication process. Stress state induced by both front-end and packaging processes has been studied based on the established methodology. Thus, potential sites for delamination are identified. For critical sites, fracture mechanics approach is applied, and energy release rate is computed in order to determine the reliability of copper/low-k interconnects. Delamination hazard is investigated in several areas of interconnects, and discussions are carried out concerning crack propagation phenomena.
Fiori et al. (Mon,) studied this question.