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A novel organization of switched capacitor charge pump circuits based on voltage doubler structures is presented in this paper. Each voltage doubler takes a dc input and outputs a doubled dc voltage. By cascading n voltage doublers the output voltage increases up to 2/sup n/ times. A two-phase voltage doubler and a multiphase voltage doubler (MPVD) structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. A comparison of the voltage doubler circuits with Dickson charge pump and Makowski's voltage multiplier is presented in terms of the area requirements, the voltage gain, and the power level. This paper also identifies optimum loading conditions for different configurations of the charge pumps. Design guidelines for the desired voltage and power levels are discussed. A two-stage MPVD was fabricated using MOSIS 2.0-/spl mu/m CMOS technology. It was designed with internal frequency regulation to reduce power consumption under no load condition.
Starzyk et al. (Thu,) studied this question.