Low-noise and high-speed charge detection in high-resolution CCD image sensors

This paper analyzes problems associated with low-noise and high-speed charge detection encountered in high-resolution image sensors. It is found that the conventional Floating Diffusion (FD) charge detection concept is inferior to the previously studied, but not frequently utilized, Floating Gate (FG) approach. A new output charge detection well reset technique and an improved biasing method allowed the design of the FG charge detection amplifier with a comparable conversion gain to FD structures but with much better noise performance at the data rates up to 40 MHz. The theoretical analysis of the FG amplifier performance, including the Correlated Pixel Clamp signal processing method, is confirmed by measurements performed on a high-resolution 1000/spl times/1000 pixel Frame Transfer CCD image sensor built using an Advanced Virtual Phase Technology. The described details of the sensor design include: (1) the over all device architecture, (2) the pixel cross section with the cross section of the lateral overflow drain antiblooming structure, (3) the dual serial register with a single output amplifier, and (4) the resistive gate reset structure for the output charge detection well. The developed image sensor does not need the conventional Correlated Double Sampling (CDS) circuit for the signal processing, since the FG detection node is sensing charge nondestructively without generation of kTC noise. The described progress in the FG charge detection approach thus opens up a possibility for future designs of distributed FG amplifiers that can theoretically reach the ultimate low-noise performance at virtually any clocking frequency.