Register renaming and dynamic speculation: an alternative approach

In this paper, we present a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instruction fetch stage instead of the decode stage, and the mechanism is designed to operate in parallel with the tag match logic used by most cache designs. It is estimated that the critical path of the mechanism requires approximately the same number of logic levels as the tag match logic, and therefore should not impact cycle time. 1 Introduction Superscalar processors attempt to exploit instruction level parallelism by issuing multiple instructions in parallel, thereby improving performance. This improvement is limited by the amount of fine-grain parallelism present in the code. Several mechanisms have been developed that increase the number of instructions that a processor can issue in parallel, thereby increasing performance. This paper focuses on two such mechanisms: register renaming and dynamic speculation. A...