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A new low voltage CMOS four-quadrant multiplier is presented. Simulation results show that, for a power supply of ±1.5 V the differential linear range is over ±0.8V with the linearity error less than 2%. The total harmonic distortion is less than 1% with the input range up to ±0.6 V. The simulated –3 dB bandwidth of this multiplier is about 12 MHz. The proposed circuit is expected to be useful in low-voltage analogue signal processing applications.
S.-I. Liu (Thu,) studied this question.