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A design and implementation of an input/output (I/O) circuit capable of simultaneous bidirectional transmission in CMOS integrated circuits are presented. Conventional techniques for improving communication bandwidth between VLSI chips use the tri-state bidirectional drivers and/or add more I/O pins to a given chip. The design of simultaneous bidirectional transmission of signals between two chips results in optimal performance while maintaining the same pin count. The circuitry has a low output-voltage swing and occupies relatively small silicon area, so that both high speed and low power dissipation are achieved. Included also is the design of a current driver that can properly terminate a given transmission line without the use of any off-chip termination resistors. The design remains functional under significant process variation. Simulation results show that the I/O circuit can be clocked with a frequency over 50 MHz under the worst-case condition for a typical 2- mu m CMOS process. This implies a bandwidth of more than 100 Mb/s per I/O pin.>
Lam et al. (Wed,) studied this question.