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Constructing algebraic polynomials using computer algebra techniques is believed to be state-of-the-art in analyzing gate-level arithmetic circuits. However, the existing approach applies algebraic rewriting directly to the gate-level netlist, which has potential memory explosion problem. This paper introduces an algebraic rewriting technique based on the and-inverter graph (AIG) representation of gate-level designs. Using AIG-based cut-enumeration and truth table computation, an efficient order of algebraic rewriting is identified, resulting in dramatic simplifications of the polynomial under construction. An automatic approach, which further reduces the complexity of algebraic rewriting by handling redundant polynomials, is also proposed.
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Cunxi Yu
Nvidia (United Kingdom)
Maciej Ciesielski
University of Verona
Alan Mishchenko
Berkeley College
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
University of California, Berkeley
University of Massachusetts Amherst
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Yu et al. (Mon,) studied this question.
synapsesocial.com/papers/69dd50430a7b4bc8c410163e — DOI: https://doi.org/10.1109/tcad.2017.2772854