Design Constraints for Series-Stacked Energy Decoupling Buffers in Single-Phase Converters

In single-phase dc-ac and ac-dc conversion, energy decoupling is needed to compensate for the instantaneous power mismatch between the ac side and the dc side. The series-stacked buffer (SSB) is a type of active energy decoupling buffer that allows a large voltage ripple on the energy buffering capacitor to improve the energy utilization ratio while actively regulating the dc-bus voltage with minimal ripple. This architecture has been demonstrated to achieve high efficiency, high power density, and excellent ripple control on the dc bus. This letter presents a set of design constraints for the SSB that describe the quantitative relation among passive components and load power level. Compared to previous works on the SSB, the new constraints accurately identify the operation limits of the SSB. A more optimized sizing solution is thus derived. The new design constraints are derived step by step and verified with simulations and experiments.