Foveros: 3D Integration and the use of Face-to-Face Chip Stacking for Logic Devices

This paper presents the key silicon features of Intel’s 3D stacking technology, Foveros, as it is used to enable logic-on-logic die stacking. A robust face-to-face die connection is enabled with a high yielding, robust microbump connection. Additionally, we describe the low resistance TSVs used for connection to the package along with their electrical properties.