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In this paper, a CNN weight parameter quantization method which is suitable for FPGA has designed. By making the weight parameter logarithm based on 2, the multiplication of convolution is simplified to shift, which is easy to be realized in FPGA. Compared with the traditional direct quantization method, the quantization efficiency of the logarithm quantization method designed is improved greatly. If the bit width of the traditional quantization method is N that the quantization bit width of the log quantization method is changed to ceil(log 2 (n-1))+1,and the processing delay of the logarithm quantization method is better than that of the direct quantization method, especially in the case of small scale bit width processing. The advantages of occupying LUTs, FFs, BRAMs and DSP48es etc hardware resources are obvious, and the processing accuracy is similar to that of the direct quantization method, which is suitable for large scale parallel accelerated operation.
Li et al. (Fri,) studied this question.