An Efficient Deep Network in Network Architecture for Image Classification on FPGA Accelerator

Image recognition and classification apps are considered to be one of the most popular apps in recent times due to its extremely important role in daily life. To improve the energy efficiency and performance of compute-demanding CNN, FPGA-based acceleration appears to be the best solution. In this article, we design and implement a hardware / software accelerator to efficiently accelerate the entificient and reusable FPGA-based accelerator that maximizes the FPGA compute capacity by exploiting the reorganization and parallelism of weights is proposed. The accelerator also supports computation of 3 3 convolutional layers and MLPs layers without interaction with the CPU. This accelerator is integrated into the tensorflow deep learning framework to provide software programmers with an easy-to-use interface so that they can declare a network definition while taking advantage of an FPGA engine. This system implemented on a Xilinx Zynq SoC using the PYNQ-Z1 platform achieves a frame rate equivalent to 5. 91 fps using 16-bit fixed point and an energy efficiency of 186. 25x the Intel® Xeon® processre CNN on FPGAs. First, we use tiling techniques to partition the input data. Second, we integrate the proposed accelerator into the tensorflow deep learning framework. We are evaluating the proposed hardware/software system and its integration with tensorflow by implementing the Deep Network In Network. The proposed accelerator achieves peak performance of 57. 6 GOPS on a Xilinx PYNQ-Z1 FPGA board. End-to-end evaluation shows performance and power savings of up to 105. 91x compared to an Intel® Xeon® CPU E5-2620 V4 under the working frequency of 200 MHz and a frame rate equivalent to 3. 42 fps using 16-bit fixed point. Using the system with a high-end FPGA shows even higher gains and performance.