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Internet of Things (IoT) has become a considerable investigation scope in different domains such as health, transportation, smart homes, and smart cities having embedded system devices attached to wireless internet infrastructure. The explosive increase in the volume and diversity of these devices and their applications is inevitably bringing many challenges to the circuit and system design. The embedded computing unit is responsible for producing significant data through utilizing efficient approaches. Therefore to achieve this on real time process, low power consumption and high precision are a demand. Arithmetic units are an essential block that occupy a major portion of the resources and dissipate a great power for computing. Different types of binary adders and multipliers are designed, implemented at the structure level VHDL. Carry propagate adder (CPA), carry save adder (CSA), carry look-ahead adder (CLA), Array multiplier, Wallace multiplier, Modified-Wallace multiplier, and modified Booth radix4 multiplier are achieved in this paper. The proposed techniques are synthesized in a standard 90-nm CMOS process, 1.0 V supply voltage with the Synopsys Design Compiler, for 16-bit, 32-bit, and 64-bit input operands at 100 MHz operating frequency. The performance evaluation results for the proposed schemes are accomplished.
Nan et al. (Sun,) studied this question.