Scaling of double-gated WS2 FETs to sub-5nm physical gate length fabricated in a 300mm FAB

We present an analysis of gate length scaling of WS2 transistors fully fabricated in a 300mm pilot line. Despite low channel mobility, I_=100 A/ m is enabled by low side contact resistance R₂=1. 3 1. 0k- m at n=3 10^13cm^-2. Hysteresis of 5m V/V at moderate electric fields is demonstrated. High single-device yield and low variability is achieved, and it is established that I₎₍ correlates mainly with mobility and less with SS and Vₓ. We demonstrate that switch-off can still be achieved with extremely scaled L₆=2nm, but significant short-gate effects occur due to thick CET and unoptimized device configuration. We show better short-gate control with connected dual gate configuration. TCAD simulations identify the main performance bottlenecks and a path towards improved device performance over Silicon FETs.