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Today's SoCs/SIPs face numerous design challenges as increased integration of system components on a single die stretches the limits of technology and design capacity. 3D integration, where multiple dies are stacked and interconnected in the vertical dimension using through-silicon vias (TSVs), is probably the best hope for carrying ICs along (and even beyond) the path of Moore's law in the 21st century. However successful adoption of 3D ICs will require among other things modifications to EDA tools to enable 3D IC design. In this paper, we identify key stages in EDA that need modification to handle 3D ICs, highlight the challenges and review existing solutions, if they exist. Whenever appropriate, at a particular stage, we also provide preferred features of the solutions necessary to enable 3D IC design with the least amount of disruption.
Chiang et al. (Thu,) studied this question.