Experimental demonstration and modeling of a ferroelectric gate stack with a tunnel dielectric insert for NAND applications

We experimentally demonstrate, for the first time, that the insertion of an Al 2 O 3 layer in the middle of the ferroelectric (FE) Hf 0.5 Zr 0.5 O 2 (HZO) stack significantly enhances the memory window (MW). For example, the MW increases from 3 V in a reference HZO gate stack without the Al 2 O 3 insert to as high as 7.3 V, representing a more than 2x improvement, in the engineered HZO-Al 2 O 3 -HZO stack with the same total thickness and write voltage ≤15 V. A numerical model of the gate stack was calibrated to the experimental data set obtained from a series of 7 gate stacks with varying HZO and Al 2 O 3 thicknesses and bias conditions. The model reveals that the Al 2 O 3 layer acts as a tunneling barrier for the trapped electrons and holes at the HZO-Al 2 O 3 interface. The direction of dipole that forms across the Al 2 O 3 layer creates an additional electric field that aligns with direction of polarization and enhances the MW. These results indicate that electron and hole trapping, as opposed to the conventional role of working against the ferroelectric effect, can be leveraged to enhance the MW in FEFETs by appropriate gate stack design. A comprehensive design space exploration of the gate stack of FEFETs, based on the model, reveals a pathway to achieving a 12 V MW while satisfying the constraints of vertical NAND flash technology: a total gate stack thickness of 20 nm and a write voltage ≤15 V.