Enhanced ARIA-based counter mode deterministic random bit generator random number generator implemented in verilog

This paper presents a study aimed at effectively implementing a deterministic random bit generator (DRBG) IP in verilog language, based on the standard encryption algorithm. By controlling the existing round generation and key generation blocks, the internal modules of the counter mode deterministic random bit generator (CTR-DRBG) were successfully implemented and operated, ensuring the secure and efficient generation of random bit sequences. The research focused on parallel operation of modules and optimized module placement to achieve improved clock frequencies. By concurrently operating two modules in the derivation and internal update modules of CTR-DRBG, the processing speed was enhanced compared to the conventional algorithm. Additionally, integrating the reseeding and initialization modules of CTR-DRBG into a single module successfully reduced size. Furthermore, this IP supports the special function register (SFR) interface. The safety of the CTR-DRBG was validated through known answer test (KAT) verification utilizing test vectors from certification. Future research should explore additional studies on CTR-DRBG operating on real FPGA or ASIC, not only using normal algorithm but also employing other block cipher algorithms.