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This paper presents the design and measurement results of a prototype integrated circuit (IC) of pixel architecture operating in single photon counting mode with real-time interpixel communication. The prototype IC is designed in the CMOS 40 nm process and its core is a matrix of 32 × 64 pixels of 50 μm pitch. Each pixel contains fast front-end analog electronics, a set of discriminators, ripple counters and digital blocks implementing relocation algorithms. These algorithms utilize interpixel communication to benefit from charge sharing effect by increasing the detector spatial resolution beyond the limit determined by pixel pitch. Using the bump-bonding technique, the IC was connected to a pixelated semiconductor detector with 400 μm thickness and tested using a 16 keV synchrotron monochromatic X-ray beam at the European Synchrotron Radiation Facility.
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Piotr Otfinowski
AGH University of Krakow
D. Magalhães
European Synchrotron Radiation Facility
P. Fajardo
European Synchrotron Radiation Facility
IEEE Transactions on Circuits & Systems II Express Briefs
Jagiellonian University
European Synchrotron Radiation Facility
AGH University of Krakow
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Otfinowski et al. (Tue,) studied this question.
synapsesocial.com/papers/68e75a0cb6db6435876d1572 — DOI: https://doi.org/10.1109/tcsii.2024.3372884
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