High‐κ Dielectric (HfO2)/2D Semiconductor (HfSe2) Gate Stack for Low‐Power Steep‐Switching Computing Devices

Abstract Herein, a high‐quality gate stack (native HfO 2 formed on 2D HfSe 2 ) fabricated via plasma oxidation is reported, realizing an atomically sharp interface with a suppressed interface trap density ( D it ≈ 5 × 10 10 cm −2 eV −1 ). The chemically converted HfO 2 exhibits dielectric constant, κ ≈ 23, resulting in low gate leakage current (≈10 −3 A cm −2 ) at equivalent oxide thickness ≈0.5 nm. Density functional calculations indicate that the atomistic mechanism for achieving a high‐quality interface is the possibility of O atoms replacing the Se atoms of the interfacial HfSe 2 layer without a substitution energy barrier, allowing layer‐by‐layer oxidation to proceed. The field‐effect‐transistor‐fabricated HfO 2 /HfSe 2 gate stack demonstrates an almost ideal subthreshold slope (SS) of ≈61 mV dec −1 (over four orders of I DS ) at room temperature (300 K), along with a high I on / I off ratio of ≈10 8 and a small hysteresis of ≈10 mV. Furthermore, by utilizing a device architecture with separately controlled HfO 2 /HfSe 2 gate stack and channel structures, an impact ionization field‐effect transistor is fabricated that exhibits n‐type steep‐switching characteristics with a SS value of 3.43 mV dec −1 at room temperature, overcoming the Boltzmann limit. These results provide a significant step toward the realization of post‐Si semiconducting devices for future energy‐efficient data‐centric computing electronics.