Leveraging High Level Synthesis for the Design of Hardware Accelerators for Model Predictive Control

This work explores the benefits of using the High-Level Synthesis paradigm for the rapid design of FPGA-based accelerators for Model Predictive Control following a top-down design strategy. Starting from a software implementation of the operations in the control loop, we focus on leveraging typical hardware directives for parallelizing the execution of computationally demanding linear algebra operations involved in optimization algorithms, to achieve low-latency real-time operation while retaining numerical accuracy of the software counterparts with reduced design effort. The performed analysis and evaluations provide insights into the performance-cost tradeoffs when optimizing the Alternating Direction Method of Multipliers algorithm. We also derive general guidelines for tuning application-specific algorithms and deploying cost-effective FPGA accelerators to fulfill requirements for control timing intervals with relatively low coding effort.