Hardware Implementation and Validation of Low-Latency LDPC

In this investigation, we developed the hardware for a low-latency low-density parity check (LDPC) decoder and validated its error-correction performance. The LDPC code was chosen as the error-correction code conforming to the international portable Internet standard IEEE 802.16e. The LL-LDPC code, implemented in this study, efficiently minimizes the number of coded calculations through the utilization of a type of Structured-LDPC code defined by the physical layer description in IEEE 802.16e. The low-delay LDPC decoder employs a parallel decoding method to mitigate the decoding delay associated with repetitive decoding. Comprising four SISO modules based on four coding repetitions in the coder, the low-delay LDPC decoder significantly reduces delay times. The four SISO modules operate in parallel, enabling simultaneous decoding and thereby decreasing the delay time by 1/4 compared to alternative approaches.