Characterizing Power and Performance Interference Scalability in the 28-core ARM ThunderX2

Nowadays, energy efficiency is a major concern in any type of processor-based device, ranging from processor servers to supercomputers, including mobile battery-fed devices. In recent years, systems based on the ARM architecture, tra-ditionally better suited for mobile and embedded systems, have increased their market share in segments commonly occupied by x86 processors. This growth is due, to some extent, to the excellent energy efficiency shown by high-performance ARM processors. Designing software and hardware energy-efficient systems requires a sound knowledge of the relationship among three main axes: component activity, power, and inter-application interference at the shared resources. This problem aggravates in many-core processors, which are ubiquitous in high-performance servers. This paper characterizes the aforementioned axes in a 28-core ARM Thunder X2 processor. Experimental results show that the performance of highly-scalable single-threaded applications is sustained regardless of the number of applications and interference introduced at the shared resources at the cost of increasing power. In contrast, low-scalable applications require much less power and experience a huge performance degradation as their number increases.