Post-Fabrication Performance and Longevity Improvement of a Phase-Locked Loop With an On-Chip Phase Noise Measurement Circuit

A 4-GHz phase-locked loop (PLL) incorporating an on-chip phase noise (PN) measurement circuit and a voltage-controlled oscillator (VCO) using an array of cross-coupled transistor pairs that can be configured using intelligent post-fabrication selection is reported. The cross-coupled pairs employ transistors with dimensions near the minimum for the process, and the post-fabrication configuration lowers its PN. The selection reduces the PLL PN at a 1-MHz offset from a 4-GHz carrier by 3. 8 dB from the worst. The PN measurement circuit not requiring an external surface acoustic wave (SAW) filter was used to measure PN of - 119 and - 128 dBc/Hz at 1-and 2-MHz offsets, respectively. These are 2–3 dB lower compared to the lowest measured using on-chip PN measurement circuits in the literature. The maximum PN measurement circuit error at 1-MHz offset is 1. 2 dB compared to signal source analyzer (E5052B) measurements. After high voltage stress that degrades PN, the performance was recovered by reselection, indicating that this design approach should also allow an increase in the VCO lifetime. This circuit is fabricated in a 65-nm CMOS technology with a chip area of 1 1. 5 mm. The on-chip PN measurement circuit consumes 7. 5 mW of dc power. This work suggests that designing for the best performance rather than the conventional approach of designing for the worst can be made practical.