Transition from Synchronous to Asynchronous Systems with Minimal Logic Changes

This paper examines the transition from syn-chronous to asynchronous microprocessor systems as a response to the physical and technological limits reached in terms of transistor size reduction and internal circuitry. The implementation of the delay-insensitive, dual-rail, 4-phase methodology in a microprocessor based on the von Neumann architecture is studied, using a technique that reduces to a minimum the changes required in the register transfer level (RTL) design, while pre-serving the designs used in synchronous logic. Simulation results show that asynchronous systems outperform their synchronous counterparts by 90.9% in terms of power consumption. This approach represents a promising perspective for the evolution of digital technology, opening up new opportunities and challenges for the future.