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The results of an experimental comparison of programs for technologically independent minimization of complexity of multilevel representations of systems of fully defined functions based on the Shannon expansion are described. The main attention is paid to the effectiveness of using, when synthesizing logical circuits, a program that implements an algorithm for solving the problem of extracting from a system of functions such subsystems for which it is advisable to carry out joint minimization of multi-level representations of subsystems in the form of Binary Decision Diagrams, called BDD-representations, and in the form of Boolean net. The complexity of the representation is estimated by the total number of literals of Boolean variables in a set of interrelated logical equations that define a system of Boolean functions. After extracting the subsystems and their joint minimization, the synthesis of logic circuits is carried out in the design library of custom digital CMOS VLSIs, the results are compared in terms of chip area and speed (time delay) on a stream of 39 industrial examples of circuits. It was found that for 20 examples, the subsystem selection algorithm allows one to obtain better solutions than joint or separate minimization of multi-level representations based on Shannon expansion (13 examples). The three best solutions are obtained by applying the well-known Espresso program for minimizing functions in the DNF class, and the three solutions are obtained by the synthesizer using the original (non-optimized) matrix representations of DNF systems of Boolean functions.
Бибило et al. (Thu,) studied this question.