Power and Delay Efficient Approximate Sparse Matrix Vector Multiplication on FPGA using HLS

High-Level Synthesis (HLS) tools have the capability of creating register-transfer level from high-level specifications by not degrading the performance. OpenCL framework uses HLS tools, enabling programmers to create standardized C-like code for both host and hardware accelerators. Energy efficient high-performance computing (HPC) systems will serve as a promising solution for the next-generation edge AI. FPGA-based accelerators are energy efficient for SpMV, a kernel for workloads with irregular memory access. For Machine Learning applications large no. of computations required with lot of data, hence resource utilization and delay efficient models needed. In this paper, initially we designed SpMV kernel with loop pipelining, different memory access patterns, and data partition which have an impact on the hardware architecture. The SpMV kernel's data access was mostly optimized, and HLS pragmas were utilized to increase the kernel's parallelism and performance. Further we developed two approximate algorithms that leverages reduction in precision and a novel packet-wise CSR matrix compression. Our evaluations show that execution time reduced by more than 20% by using Array Partition with Pipeline on the kernel and performance improved by 2x times with approximate models.