A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2 m )

Binary polynomial multipliers impact the overall performance and cost of elliptic curve cryptography (ECC) systems. Multiplication algorithms with subquadratic computational complexity are widely used to reduce area requirements and improve the delay of ECC cryptographic hardware. This work presents an elliptic curve scalar point multiplication (SPM) processor implementation using a novel classification of improved overlap-free multipliers targeting applications in the Internet of Things (IoT) devices. The proposed multipliers combine the advantages of fewer partial products and the overlap-free reconstructions which results in better recurrence and improved performance. The proposed multipliers and point multiplication hardware were designed, implemented, and tested on FPGA. The implemented processor presents a reasonable trade-off between speed and area consumption, and the design compares favorably with the previous designs in terms of area-delay product.