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As the usage of portable devices continues to surge, optimizing power efficiency becomes paramount for extended battery life. Within digital devices, Arithmetic Logic Unit (ALU) within the central processing unit (CPU) stands as a major power consumer. To overcome this problem Quantum-dot Cellular Automata (QCA) cells are possible and alternative solution to mitigate area, circuit latency and power consumption. QCA cells are nano-sized devices, exhibit promising traits of low power dissipation and minimal latency. Implementing reversibility as the foundation of the design as well as the integration of QCA into circuit designs, offering a potential replacement for traditional CMOS technology. This study introduces a Reversible ALU(RALU) architecture integrated with QCA, presenting a viable solution for processors as well as ALU based circuits in low power applications due to its compactness, power efficiency, and capability of designing streamlined instruction set architecture. Furthermore, the designed architecture employs reversible gates such as Feynman Gate (FG), Toffoli Gate (TG), Fredkin Gate (FRG) and Peres Full Adder Gate (PFAG). In this paper, we have introduced QCA model of these gates and obtain significant improvement in the performance parameters over the existing designs. The proposed QCA based RALU demonstrates a remarkable 57% enhancement in packing density, leading to an impressive 59% average improvement in area utilization compared to existing work. Also, the design has achieved a maximum overall improvement of 39% over the existing designs. This approach has promising implications for advanced computing, setting a new standard for energy-efficient processing in the age of portable devices.
Dey et al. (Fri,) studied this question.