Heterogeneous Hardware Acceleration Methodology on SoC FPGA Using High Level Synthesis

In recent years FPGA has not only been used for fast prototyping of IC design but more adopted to high-level and complex system integration for field applications such as machine learning, data processing, or Fintech using High-level synthesis (HLS). The HLS, sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior. In this talk, we will give a short lecture about what is HLS and what benefits it can contribute to heterogeneous hardware acceleration, and last but not least real applications and examples.