Architectural Security and Trust Foundation for RISC-V

Modern System-on-Chips (SoC) rely on Trusted Execution Environment (TEE) to ensure the integrity and confidentiality of sensitive information by providing a secure environment for data processing. Serval TEE enablement with many mechanisms and architectures has been proposed for ARM-based computing devices, thus, presenting a rich body of literature. In counterpart, RISC-V lacks ratified TEE specifications and hence an effective system-wide security approach. Given an increasing number of vendors and Original Equipment Manufacturers (OEM) now plan to adopt the RISC-V in their products, this paper fills the gap and proposes a reference security and trust architecture enforced by TEE to allow the building of new security solutions and applications. We evaluate the work against current industry security requirements and practices and present comprehensive research with a promising direction. To the best of our knowledge, this is the first work exploring, proposing, analyzing, and evaluating complete security enablement for RISC-V with a final goal of delivering enhanced security at a lower cost to the smart devices market based on RISC-V.