Design and Analysis of Ternary Full Adder Based on FinFET Models

In the field of digital system design, the introduction of multivalue logics has shown to be beneficial as it reduces circuit complexity and improves energy efficiency. Ternary logic is usually seen as an innovative approach in the realm of multivalue logic. This article presents a comprehensive overview of the design of a ternary full adder using 18nm FinFET technology, implemented via the use of the Virtuoso tool offered by Cadence. The evaluation of the full adder's performance is carried out by a comparison of the results obtained using SVT and HVT FinFET models. The obtained simulation results reveal power consumption values of 124. 9 and 113. 6 μW, transient delay values of 180. 1 and 180. 7 ns, and power delay product values of 22. 49 and 20. 64 (x 10_ 12 J) for the SVT and HVT FinFET models, respectively. The proposed design of a ternary full adder can be used for processing ternary encoded signals and designing of ternary arithmetic circuits for ternary computers.