Impact of Clock-Gating on ALU Optimized RISC-V Microarchitectures for Low Power Applications

Due to huge demand in the general purpose processors for the applications across industries, there is a global attempt to optimize the power consumed to make it sustainable for low power applications. The proposed work aims to provide a conclusive report on reduction in switching power of a Single Cycle and Pipelined RISC- V core with focus also on adder and the multiplier circuits with optimized power consumption. The matrix multiplication assembly code is run to measure the power consumption. With the core synthesized using Cadence Genus with the saed-90nm technology node. The average power reduction of 56.9% in the switching power is observed in Single Cycle microarchitecture and 23.4% in 5-stage pipelined RISC-V micro architecture due to application of Discrete clock-gating using the Synthesis tool - Cadence Genus.